1. Field
The present invention relates to a clock generator and a clock generating method.
2. Background
A clock generator has been widely used to provide a microprocessor, a digital signal processor, an integration circuit and the like with a system clock. A clock generator using a phase locked loop (PLL) has been often used as a related art clock generator. The PLL clock generator generally includes a phase detector for detecting a phase difference between a clock signal provided by a frequency generator and a clock signal outputted from a frequency divider, a loop filter, a voltage controlled oscillator and a frequency divider. The loop filter is for removing a high frequency component from the phase difference detected by the phase detector, and the voltage controlled oscillator is for changing a frequency of an output clock signal according to the phase difference outputted by the loop filter. The frequency divider is for dividing the frequency of the output clock signal by N (e.g., N is a natural number) to output the divided output clock signal. Such a PLL clock generator has advantages including the frequency of the output clock signal is N times that of the input clock signal by including the frequency divider. Further, the frequency divider can be implemented by using a counter so that the implementation of the frequency divider is simple and the N value may be easily changed. However, there are also disadvantages including at least that a restored clock signal has an increased phase noise because the voltage controlled oscillator of the PLL clock generator employs a positive feed back circuit. Further, the phase noise is seriously increased if a noise of a supply voltage increases.
A delay locked loop (DLL) clock generator can include a phase detector for detecting a phase difference between a clock signal provided by a frequency generator and a clock signal outputted from a voltage controlled delay line, a loop filter and a voltage controlled delay line. The loop filter is for removing a high frequency component from the phase difference detected by the phase detector, and the voltage controlled delay line is for changing a delay of an input clock signal according to the phase difference outputted by the loop filter to generate an output clock signal. Since such a DLL clock generator does not include a voltage controlled oscillator, the DLL clock generator includes advantages in that the above-described disadvantages occurring in the PLL clock generator can be reduced or prevented. However, disadvantages of the DLL clock generator include the DLL clock generator can generate only an output clock signal having the same frequency as that of the clock signal provided by the frequency generator. U.S. Pat. No. 6,784,707 discloses a conventional DLL clock generator that addressed the above-described disadvantages by including a frequency multiplier for outputting a clock signal having a frequency that is N/2 times that of a clock signal transmitted from a frequency divider by using a plurality of clock signals. The plurality of clock signals are outputted from a voltage controlled delay line and each clock signal has a different delay. Herein, N means the number of delay cells included in the voltage controlled delay line. However U.S. Pat. No. 6,784,707 has disadvantages because N delay cells are required to obtain a frequency of N/2-tuple and the number of transistors included in the frequency multiplier has to be increased in proportion to N. That is, the complexity of the frequency divider of the PLL clock generator increases approximately in proportion to log2N and the complexity of the frequency multiplier disclosed in U.S. Pat. No. 6,784,707 also increases in proportion to N. Therefore, one drawback in the frequency generator of U.S. Pat. No. 6,784,707 is a large number of transistors are required to make a variety of frequencies.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.